For system LSI, etc., circuits for executing multiple functions are integrated on a semiconductor chip. Usually, different circuits operate on different voltage levels corresponding to the purposes and characteristics. For example, as shown in FIG. 10, semiconductor chip 100 for use in mobile phones, PDAs, etc. contains core circuit 104 that operates at a low voltage of about 1.8 V fed from low voltage source 102, and driver 112 that operates at a high voltage of about 20 V fed from high voltage source 110. Driver 112 needs a high voltage in order to drive a liquid crystal or other display. In order to ensure output of the high-voltage driving signal as a response to low voltage level input signal IN from core circuit 104, level shift circuit 120 is set between said two circuits.
FIG. 11 is a diagram illustrating the constitution of a conventional level shift circuit of the prior art. For example, this type of level shift circuit is disclosed in FIG. 32 of Patent Reference 1. The level shift circuit has a pair of inverter connected P type MOS transistors P1, P2 and N type MOS transistors N1, N2 between VDDH and ground potential (GND). The gates of transistors P1, P2 are mutually cross coupled to output nodes XOUT, OUT of the other side, and input signals IN, XIN that are complementary to each other are fed to the gates of transistors N1, N2. Input signals IN, XIN are signals on the low voltage level (VDD–GND).
FIG. 12 is a timing chart illustrating the operation of the level shift circuit shown in FIG. 11. When high level (VDD) and low level (GNG) signals are input as input signals IN, XIN, from output terminal OUT, a high level signal (VDDH) obtained by level shift of the voltage is output. When the input signal is inverted, as a response, the output signal from output terminal OUT is inverted.
Patent Reference 1: Japanese Kokai Patent Application No. 2001-298356
However, the conventional level shift circuit has the following problems. FIG. 13 is a diagram illustrating an example of the level shift circuit carried on a conventional semiconductor chip. On this chip, there are the following parts: battery 200 that feeds the high voltage (VDDH), reference voltage generator 210 that is fed high voltage from battery 200, voltage regulator 220, logic circuit 230 and level shift circuit 240. Reference voltage generator 210 generates reference voltage (Vref) from the high voltage, and feeds it to voltage regulator 220. On the basis of the reference voltage (Vref), voltage regulator 220 generates a low voltage (VDD) of 1.8 V, and outputs it to logic circuit 230. As a response to the input to input terminal INA, logic circuit 230 feeds complementary low voltage input signals IN, XIN to level shift circuit 240. As a response to complementary input signals IN, XIN, level shift circuit 240 outputs the high voltage signal from output terminal OUT.
FIG. 14 is a timing chart illustrating the operation. A high voltage is fed from battery 200. Then, after a prescribed period, a low voltage is fed from voltage regulator 220. That is, there is a delay or time difference between time T1 when the high voltage is fed and time T2 when the low voltage is fed. VDD is not fed to logic circuit 230 during time T1–T2, so that complementary input signals IN, XIN become unstable. The high voltage (VDDH) is first fed to level shift circuit 240. As complementary input signals IN, XIN become unstable, the output from the output terminal during this period becomes unstable, and this leads to problems in the circuit operation. For example, when the level shift circuit is used for the chip select signal, reset signal, etc., if there the output is unstable state, erroneous operation may occur, which is a serious problem.